Posted on: 17/06/2025
Job Title : Verification Engineer Digital
Experience Level : 4 to 10 Years
Work Location : Bangalore (Work From Office 5 Days a Week)
Employment Type : Full-Time
About the Role :
Key Responsibilities :
- Utilize object-oriented verification methodologies (System Verilog, UVM).
- Collaborate with designers to integrate design changes into the verification environment.
- Develop and manage verification testbenches and reusable test environments.
- Work with analog and architecture teams for mixed-signal integration and modeling.
- Perform simulations at various PVT corners using gate-level netlists.
- Generate VCD files for power analysis.
- Implement and analyze code coverage, functional coverage, and RAL-based verification.
- Run ATPG simulations and have a good understanding of DFT concepts.
- Use scripting languages (Perl, Python, Shell) to automate verification workflows.
- Contribute to bring-up and lab-based validation using FPGA platforms.
- Support customer queries, debug issues, and ensure timely closure.
Required Skills & Experience :
- 4 to 15 years of hands-on experience in Digital/Mixed-Signal Verification.
- Proficient in System Verilog and UVM.
- Experience in scripting languages : Perl, Python, Shell.
- Strong understanding of digital basics, DFT, RAL, coverage metrics, and ATPG simulations.
- Exposure to power-aware simulation and VCD generation.
- Experience with FPGA-based validation and silicon bring-up preferred.
- Proven ability to manage multiple verification blocks and tasks efficiently.
- Strong debugging and analytical skills.
Preferred Background :
- Prior experience working on mixed-signal verification projects.
- Not looking for candidates from consulting/service-based backgrounds.
Work Mode & Location :
Location : Bangalore
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Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1498236
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